1. Field of the Invention
The present invention relates to a charge transfer device and more particularly to the charge transfer device that can be suitably used in an image pickup apparatus such as a television camera or a like.
The present application claims priority of Japanese Patent Application No. 2000-275708 filed on Sep. 11,2000, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 7 is a schematic block diagram for showing configurations of a conventional charge transfer device disclosed in Japanese Patent No. 2666522. The disclosed charge transfer device includes a CCD (Charge Coupled Device) 1, a floating diffusion region 2, depletion type n-channel MOS (Metal Oxide Silicon) transistors 3 to 5 and enhancement type n-channel MOS transistors 6 to 8.
The floating diffusion region layer 2 is formed using a pn-junction islands-structured semiconductor region and is adapted to convert a signal charge (electron) injected into one terminal (charge injecting point P) of the floating diffusion region layer 2 after having been transferred through a charge transfer region (not shown) in the CCD 1 and after having passed a channel under an output gate (not shown), into a voltage. A capacitance of the floating diffusion region layer 2, in order to enhance a conversion rate at which the above signal charge is converted into the voltage, is ordinarily set at as small as about 7 fF (femto Farad) . The MOS transistor 3 operates as a resetting unit to eject the signal charge accumulated in the floating diffusion region 2 and to reset a voltage VP at the charge injecting point P to a constant level, to a gate of which a reset pulse xcfx86R is fed and to a drain of which a reset drain voltage VRD is applied and a source of which is connected to the charge injecting point P.
The MOS transistors 4, 6, and 7 make up a first stage source follower 9 in which the MOS transistor 6 functions as a driving transistor, the MOS transistor 4 functions as a load transistor, and the MOS transistor 7 functions as the load transistor only when it is turned ON. An input terminal of the source follower 9, that is, to a gate of the MOS transistor 6, is connected to the charge injecting point P. A drain of the MOS transistor 6 is applied a supply voltage VDD. A gate and source of the MOS transistor 4 and a source of the MOS transistor 7 are grounded and to a gate of the MOS transistor 7 is applied the reset pulse xcfx86R.
The MOS transistors 5 and 8 make up a second stage source follower 10 in which the MOS transistor 8 functions as a driving transistor and the MOS transistor 5 functions as a load transistor. An input terminal of the source follower 10, that is, a gate of the MOS transistor 8 is connected to an output terminal of the source follower 9, that is, a connection point among the source of the MOS transistor 6, drain of the MOS transistor 4, and the drain of the MOS transistor 7. To a drain of the MOS transistor 8 a supply voltage VDD is applied. A gate and source of the MOS transistor 5 are grounded. From an output terminal of the source follower 10, that is, from a connection point between a source of the MOS transistor 8 and a drain of the MOS transistor 5 is an output voltage VOUT.
Next, operations of the above charge transfer device will be described. The signal charge (electron) transferred through the charge transfer region and accumulated under a transfer electrode, after having passed through the channel under the gate, is injected into the charge injecting point P of the floating diffusion region 2. A voltage at the charge injecting point P that has changed by the injection of the signal charge into the charge injecting point P, after being amplified by each of the first stage and second stage source followers 9 and 10, is output as the output voltage VOUT. The output voltage VOUT is further amplified about ten-fold and, after having been sample-held, is converted into digital data by an AD converter (not shown).
Then, when the reset pulse xcfx86R goes high, the MOS transistor 3 is turned ON and a source voltage of the MOS transistor 3, that is, a voltage VP at the charge injecting point P and the reset drain voltage VRD that has been applied to a drain of the MOS transistor 3 become the same. At this point, in the source follower 9, since the MOS transistor 7 is turned ON by the supply of the xe2x80x9chighxe2x80x9d reset pulse xcfx86R and the MOS transistors 4 and 7 forming the parallel circuit, function as the load transistors, more currents flow through the MOS transistors 4 and 7, compared with the case in which only the MOS transistor 4 functions as the load transistor, thus causing an offset current of the source follower 9 to be reduced.
Next, when the reset pulse xcfx86R goes low, the MOS transistor 3 is turned ON and a state at the charge injecting point P becomes floating. At this point, in the source follower 9, since the MOS transistor 7 is turned OFF by the supply of the xe2x80x9clowxe2x80x9d reset pulse xcfx86R and only the MOS transistor 4 functions as the load transistor, less current flows through the MOS transistor 4, compared with the case in which the MOS transistors 4 and 7 forming the parallel circuit, function as the load transistor, thus causing the offset voltage of the source follower 9 to be boosted.
FIG. 8A is a cross-sectional view of the floating diffusion region 2 and related components connected thereto to explain principles of occurrence of a reset field-through noise described later. FIG. 8B is a diagram showing potentials of the components making up the floating diffusion region 2. In some cases, as shown in FIG. 7 and FIGS. 8A and 8B, since a coupling capacitor C1 exists between a gate 3a of the MOS transistor 3 and the charge injecting point P, electrons accumulated under the gate 3a are returned back to the floating diffusion region 2 through this coupling capacitor C1. Moreover, the capacitance of the floating diffusion region 2, as described above, is ordinarily set at as low as 7 fF to enhance the conversion rate to convert the signal charge to the voltage and, structurally, its impedance is very high. Moreover, as shown in FIG. 7 and FIGS. 8A and 8B, a coupling capacitor C2 exists between the gate and the source of the MOS transistor 6. As shown in FIG. 8A, an N-type well 12 is formed on a P-type well or P-type substrate 11 and a gate oxide film (not shown) and polycrystalline silicon film (not shown) are sequentially formed on a top surface of the N-type well 12 and, by performing patterning operations on them films, the CCD 1, floating diffusion region 2, and MOS transistor 3 are fabricated.
Due to the above three factors, the voltage VP at the charge injecting point P is changed in synchronization with switching operations of the MOS transistor 3 caused by the supply of the reset pulse xcfx86R, A noise induced by this change in the voltage is called the xe2x80x9creset field-through noisexe2x80x9d. Though this reset field-through noise is superimposed on the output voltage VOUT, as described above, since only when the reset pulse xcfx86R goes high, the MOS transistor 7 functions as the load transistor and the offset voltage of the source follower 9 is lowered, the reset field-through noise superimposed on the output voltage VOUT, since it is reduced by the MOS transistor 7, becomes small, compared with the reset field-through noise being produced in the voltage VP at the charge injecting point P.
In the conventional charge transfer device as described above, as the MOS transistor 5 making up the second stage source follower 10, the depletion type MOS transistor is used. Since such the depletion type MOS transistor has the property that the current to be controlled does not flow at an interface surface of the gate oxide film thereof but flows at a deeper portion, the current control is structurally difficult and the fabrication of the charge transfer device that can provide constant operating points is difficult accordingly. Therefore, the conventional charge transfer device presents a problem in that an amount of the reset field-through noise to be reduced varies in each of the fabricated charge transfer devices.
Moreover, in the conventional charge transfer device, the depletion type MOS transistor and enhancement type MOS transistor with configurations differing from each other are used as the MOS transistors 4 and 7 functioning as the load transistor in the first stage source follower 9. Therefore, also in this case, the amount of the reset field-through noise to be reduced varies in each of the fabricated charge transfer devices due to variations in threshold values or in gate widths of each of the MOS transistors 4 and 7. This presents another problem.
Furthermore, in the conventional charge transfer device, since the reset pulse xcfx86R is applied to the MOS transistor functioning as the load transistor in the first stage source follower 9, the output voltage from the source follower 9 is changed and this change affects the floating diffusion region 2 through the coupling capacitor C2. This causes a mustache-shaped pulse-like noise to be produced in the signal having the output voltage VOUT at a change point of the reset pulse xcfx86R; thus presenting still another problem.
In view of the above, it is an object of the present invention to provide a charge transfer device capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise.
According to a first aspect of the present invention, there is provided a charge transfer device including:
a floating diffusion region to convert a signal charge transferred from a charge coupled device into a voltage;
a resetting unit to eject a signal charge accumulated in the floating diffusion region in response to a reset pulse;
a first source follower to current-amplify the voltage; and
a second source follower in which a load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first source follower.
In the foregoing, a preferable mode is one that wherein includes a voltage amplifier to voltage-amplify the output voltage of the first follower and to feed the amplified voltage to the second source follower.
Also, a preferable mode is one that wherein includes a delay circuit to delay the reset pulse by a fixed time interval and to feed the reset pulse to the second source follower.
Also, a preferable mode is one wherein the delay circuit is made up of a resistor and a capacitor.
Also, a preferable mode is one wherein the delay circuit is made up of inverters connected in series in a plurality of stages.
Also, a preferable mode is one wherein delay time set by the delay circuit is determined based on delay time in the first source follower and on delay time in the resetting unit.
Also, a preferable mode is one wherein the delay time set by the delay circuit is determined based on delay time in the first source follower, delay time in the resetting unit, and delay time in the voltage amplifier.
Also, a preferable mode is one wherein the second source follower is made up of a driving transistor, first load transistor, and second load transistor which function only when the reset pulse or delayed reset pulse is applied.
Also, a preferable mode is one wherein the second load transistor is an enhancement type n-channel MOS transistor doped with p-type impurity.
Also, a preferable mode is one wherein the first and second load transistors are enhancement type n-channel MOS transistors doped with p-type impurity wherein the first and second load transistors have same gate widths and operate at same threshold voltages and wherein a supply voltage is applied to a gate of the first load transistor and the reset pulse or the delayed reset pulse having approximately a same amplitude as that of the supply voltage is applied to a gate of the second load transistor.
Furthermore, a preferable mode is one wherein a gate width of the second load transistor is designed so that a reset field-through noise occurring based on operations of the resetting unit is reduced to a predetermined amount.
According to a second aspect of the present invention, there is provided a charge transfer device including:
a floating diffusion region to convert a signal charge transferred from a charge coupled device into a voltage;
a resetting unit to eject a signal charge accumulated in the floating diffusion region in response to a reset pulse;
a first source follower to current-amplify the voltage;
a second source follower in which a load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first source follower;
a voltage amplifier to voltage-amplify the output voltage of the first follower and to feed the amplified voltage to the second source follower; and a delay circuit to delay the reset pulse by a fixed time interval and to feed the reset pulse to the second source follower.
With the above configurations, since the charge transfer device of the present invention is provided with the floating diffusion region used to convert the signal charge transferred from the CCD into the voltage, the resetting unit used to eject the signal charge accumulated in the floating diffusion region in response to the reset pulse, the first stage source follower used to current-amplify the voltage and the second stage source follower in which the load is changed in response to the reset pulse and which is used to current-amplify the output voltage of the first stage source follower, the reset field-through noise can be reduced in a stable manner without being affected by changes in characteristics of the transistors and without the occurrence of the mustache-shaped pulse-like noise.